Developing a Standard Cell Library for Sub - threshold Source - Coupled Logic

2 ACKNOWLEDGMENTS I am grateful to many people who supported and encouraged me during the work leading to this master project. I would like to specially thank Prof. Y. Leblebici, the director of Microelectronic Systems Laboratory (LSM), for his extensive support during master study and guiding me to select worthwhile research topics for both semester and master projects. I am grateful to him and to other professors and colleagues at LSM for providing an enjoyable environment. Special thank goes to Mr. Tajalli and Mr. Badel for guiding me through all stages of the project. I really appreciate their help and invaluable advices. Finally, I would like to thank my family for their interest and never-ending support during my studies. 3 ABSTRACT Power consumption is one of the main concerns in design of modern integrated circuits. The trend for implementing the required functionality using digital circuits has made the design of ultra-low power logic circuits very desirable. Sub-threshold Source-Coupled Logic (STSCL) technique is a novel method that could be used to design ultra-low power circuits operating in sub-threshold regime. In this technique, the load and the source-coupled nMOS transistors are biased in Weak Inversion (WI). The circuits designed using the STSCL technique can operate over a wide range of frequency. An interesting advantage of this technique is that the speed and power consumption of such circuits can be simply adjusted by altering the bias current of the gates without the need to resize the devices. In fact, as long as the nMOS devices remain in WI, logic evaluation will be performed correctly. In this work, design and characterization of a standard cell library for the STSCL circuits is presented. As the existing tools cannot handle the circuits with differential input/output ports, a unique method is employed to create so called fat cells out of the STSCL cells. These cells are treated exactly like their CMOS counterparts by the tools. When placement and routing of a design is finished, the fat wires are splitted into differential ones and the fat cells are replaced by corresponding cells with differential input/output ports. An FIR filter, as a demonstration circuit, is finally synthesized and implemented using the STSCL library cells to show the capabilities of the mentioned technique. 4 CONTENTS